 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Preliminary Data Sheet MAX2980 HomePlug Analog Front End including ADC, DAC, filters, and line driver for power line communications. The MAX2980 HomePlug Power Line Analog Front End (AFE) integrated circuit is a state-of-the-art CMOS device, which delivers high performance and low cost. This highly integrated design combines the analog-to-digital converter (ADC), digital-to-analog converter (DAC), signal conditioning, and power line driver. The MAX2980 substantially reduces previously required system components, while meeting the HomePlug V1.0 standard. This device interfaces with any companion Digital PHY integrated circuit (IC) to provide a complete HomePlug solution. The advanced design of the MAX2980 allows operation without external control, enabling simplified connection to a variety of HomePlug Digital PHY ICs. Additional power reduction techniques can be employed through the use of various control signals. The MAX2980 is specified over the 0C to +70C commercial temperature range and is offered in a 64-pin LQFP package. can be employed through the use of various control signals. Applications High Speed Data over Powerline (SOHO) Audio/Video Transmission over Powerline Voice/Modem Transmission over Powerline Delivering Broadband Access (PLC) Powerline-to-WiFi Bridge Powerline-to-DSL Bridge Powerline-to-Ethernet Bridge Powerline-to-USB Bridge Industrial Automation (Monitoring and Control) Home Automation (Smart Homes) Security (Cameras) MAX2980 HomePlug Analog Front End Power Line Interface Features: * Fully Integrated Line Driver and Receiver * Seamless Interface to Digital PHY ICs * 10-Bit ADC and DAC with 50 MHz Sampling * 52dB Adaptive Gain Control * -139dBm/Hz Input Referred Noise Density * Transmit Output Spectral Power Density of -52dBm/Hz into 50 * 3.0V to 3.6V I/O * 270mA in RCV Mode and/or 150mA in XMT Mode at 3.3V * 64-Pin LQFP Package PART TEMP. RANGE 0C to +70C MAX2980 AFE System Block Diagram MAX2980 LNA HPF w w w .d ta a he s t4 e LD .c u om BUF LPF AGC RX ADC MUX LPF TX DAC Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 1 www..com PINPACKAGE 64 LQFP ELECTRICAL CHARACTERISTICS (AVDD = DVDD3 = +3.3V, DVDD = VREGOUT, AGND = DGND = SHDN = 0, TA = 0C to 70C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Operating Supply Voltage Range SYMBOL AVDD, DVDD3 DVDD CONDITIONS MIN 3.0 Because DVDD is connected to Veregout, we can remove this line !!!!!!!! Receive Mode Normal Operation Transmit Mode Receiver Disabled, /SHRCV\ = high TBD 2.5 270 280 mA 155 TBD VREGOUT It needs capacitors probably! 2.5 1.29 VOH VOL 2.4 0.4 A V V TYP MAX 3.6 TBD UNITS V V Quiescent Supply Current IDD Shutdown Supply Current Regulator Output Bandgap Voltage Output Voltage High Output Voltage Low V V LOGIC INPUT CHARACTERISTICS Input High Voltage VIH 2.0 0.8 VIH = VDD VIL = 0 -10 +10 V V A A Input Low Voltage VIL Input Leakage current IIH High Input Leakage current IIL Low INPUT AND OUTPUT CLAMPS (TBD) Input Clamp Voltage Negative Rail, ICL = Positive Rail, ICL = Negative Rail, ICL = Output Clamp Voltage Positive Rail, ICL = ANALOG-to-DIGITAL CONVERTER (ADC) CHARACTERISTICS Resolution N -18mA 18mA -18mA 18mA 10 -0.8 +0.8 -0.8 +0.8 V V Bits 2 1 LSB LSB dB Bits Integral Nonlinearity INL Differential DNL Nonlinearity Two-Tone Third-Order 2-tones at 17MHz and 18MHz, IM3 Distortion 1VPP, Differential. Effective Number of ENOB Bits DIGITAL-to-ANALOG CONVERTER (DAC) CHARACTERISTICS Resolution N Integral Nonlinearity INL Differential DNL Nonlinearity Two-Tone Third-Order 2-tones at 17MHz and 18MHz, IM3 Distortion 1VPP, Differential. Effective Number of ENOB Bits RECEIVER CHARACTERISTICS Common-Mode Voltage Pins PLIP/PLIN Input Noise Input Impedance Two-Tone Third-Order Distortion Maxim Confidential FA 55 9.5 10 1.5 0.5 42 9 Bits LSB LSB dB Bits 1.62 -139 170 50 V dBm/Hz dB ZIN IM3 Between pins PLIP and PLIN 2-tones at 17MHz and 18MHz, 1VPP, Differential. This information is subject to change without notice. MAX2980_DS_A Page 2 Gain Control Range AGC Frequency Accuracy TRANSMITTER CHARACTERISTICS Common-Mode Voltage Output Impedance ZOUT Short Circuit Current ISC Output Power Spectral Density Two-Tone Third-Order Distortion Output Drive PSD IM3 -9 TBD Pins PLOP/PLON 1.59 44 TBD dB TBD V mA 2.5 300 Pre driver gain = 3dB Pre driver gain = 1dB Pre driver gain = -6dB 2-tones at 17MHz and 18MHz, 1VPP, Differential. RL = 50, -54.55 -55.9 -63.13 42 10 dBm/Hz dB TIMING CHARACTERISITICS (Figure 1) (AVDD = DVDD3 = +3.3V, DVDD = VREGOUT, AGND = DGND = SHDN = 0, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER CLK Frequency CLK Tolerance CLK Fall to ADC Data Output Valid Time CLK Fall to DAC Data Latch Time SYMBOL CONDITIONS MIN -25 tADCO tDACI Note 2 Note 2 -3 -2 2 3 TYP 50 MAX +25 7 8 UNITS MHz ppm ns ns MAX2980 Pin Description PIN 1, 5, 9, 10, 13, 17, 28, 32, 52, 53,56,57 2, 6, 12, 15, 16, 29, 54, 55, 60 3 4 7 8 11 14 18 19, 26, 49 20, 27, 34, 40, 47, 50 21 22 23 NAME AGND Analog Ground Analog Power-Supply Voltage. AVDD supply range is 3.0V to 3.6V. Bypass AVDD with a TBDF capacitor to AGND. AC Power Line Positive Input AC Power Line Negative Input External Capacitor Connection. Connect a 10nF Capacitor from CSG to AGND. External Resistor Connection. Connect a 25k resistor from EXT to AGND. AC Power Line Positive Output AC Power Line Negative Output Voltage Regulator Output. Connect VREGOUT to DVDD for normal operation. Digital 2.5V Voltage Input. Connect to VREGOUT for normal operation. Digital Ground Serial Data Input and Output Serial Clock Input Receiver Shut-Down Control. Drive /SHRCV\ high to power down receiver. Drive low for normal operation. FUNCTION AVDD PLIP PLIN CEXT REXT PLOP PLON VREGOUT DVDD DGND SDI/O SCLK /SHRCV\ Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 3 24 ENREAD 25 30, 37, 41, 44 CS DVDD3 31 33 CLK DAD9 35 DAD8 36 DAD7 38 DAD6 39 DAD5 42 DAD4 43 DAD3 45 DAD2 46 DAD1 48 DAD0 51 FREEZE 58, 59 61 I.C. ENTX 62 63 SWR /RESETIN\ 64 SHDN Read Mode Enable Control. Drive ENREADhigh to place the DAD[9:0] bi-directional buffers in read mode. Data are transferred from the Digital PHY to the AFE DAC. ENREAD signal frames the transmission. Active-High Carrier Select Input. Drive CS high to initiate the internal timer. Digital Power-Supply Voltage. DVDD3 supply range is 3.0V to 3.6V. Bypass DVDD3 to DGND with a TBDF capacitor as close to pin as possible. 50MHz System Clock Input DAC/ADC Input/Output MSB Data Bit . Input/Output of 10bit, 50MHz bi-directional digital-to-analog and analog-todigital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 8. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 7. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 6. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 5. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 4. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 3. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 2. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 1. Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output LSB Data Bit . Input/Output of 10-bit, 50MHz bi-directional digital-to-analog and analog-to-digital converter. Data is in binary format. Active-High Freeze Mode Enable. Drive FREEZE high to place the AGC adaptation in freeze mode. Drive FREEZE low, if the the signal is not available for the companion baseband chip. Internally Connected. Leave these pins floating. Active-High Transmit Enable. Drive ENTX high to enable the transmitter. Drive ENTX low to place transmitter in tristate. Active-High Register Write Enable. Drive SWR high to place the registers in write mode. Active-Low Reset Input. Drive /RESETIN\ low to place the MAX2980 into reset mode. Set CLK in free-running mode during a reset. The minimum reset pulse width is 100ns. Active-High Shutdown Input. Drive SHDN high to place the MAX2980 into shutdown mode. Drive low for normal operation. Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 4 MAX2980 Pin Diagram RESETIN 51 FREEZE /SHDN\ ENTX AGND 50 DGND 57 AGND 56 AGND 53 AGND SWR AV DD AV DD AV DD I.C. 64 63 62 61 60 59 58 I.C. TOP VIEW 55 54 52 AGND 1 AV DD 2 49 DV DD 48 47 46 45 44 43 42 41 DAD0 DGND DAD1 DAD2 PLIP 3 PLIN 4 AGND AV D D C EXT R EXT AGND 5 6 7 8 9 DV DD3 DAD3 DAD4 MAX2980 DV DD3 DGND DAD5 DAD6 40 39 38 37 36 35 34 33 AGND 10 PLOP 11 AV DD 12 DV DD3 DAD7 DAD8 DGND DAD9 AGND 13 PLON 14 AV DD AV DD 15 16 17 V REGOUT 18 19 DGND 20 21 22 23 24 25 DV DD 26 DGND 27 28 29 DV DD3 30 31 AGND AGND /SHRCV\ ENREAD TQFP ABSOLUTE MAXIMUM RATINGS AVDD to AGND ..............................................................-0.3V to +3.9V DVDD3_ to DGND ......................................................... -0.3V to +3.9V DVDD to DGND........................................................-0.3V to +TBDV AGND to DGND......................................................-0.3V to +0.3V All Other Pins........................................................-0.3V to (VDD + 0.3V) Current Into Any Pin.........................................................100mA Short-Circuit Duration (VREGOUT to AGND)....................Continuous <> Continuous Power Dissipation (TA = +70C) 64-Pin LQFP (derate TBDmW/C above +70C)............................TBDmW < Maxim Confidential FA AGND CS SDI/O SCLK DV DD AV D D CLK 32 This information is subject to change without notice. MAX2980_DS_A Page 5 Detailed Description The MAX2980 HomePlug Power Line Analog Front End (AFE) integrated circuit is a state-of-the-art CMOS device, which delivers high performance and low cost. This highly integrated design combines the analog-to-digital converter (ADC), digital-to-analog converter (DAC), signal conditioning, and power line driver as shown in the block diagram of Figure 1. The MAX2980 substantially reduces previously required system components, while meeting the HomePlug V1.0 standard. This device interfaces with any companion Digital PHY IC to provide a complete HomePlug solution. The advanced design of the MAX2980 allows operation without external control, enabling simplified connection to a variety of HomePlug Digital PHY chips. Additional power reduction techniques can be employed through the use of various control signals. Receive Channel The receiver analog front end consists of a low-noise amplifier (LNA), a high-pass filter (HPF), a lowpass filter (LPF), and an automatic gain control circuit (AGC). An analog-to-digital converter (ADC) block samples the AGC output. The ADC communicates to the Digital PHY Chip through a MUX block. The LNA reduces the receive channel input-referred noise by providing some signal gain to the AFE input. The filter blocks remove unwanted noise, and provide the anti-aliasing required by the ADC for accurate sampling. The combination of a low-pass filter and a high pass filter keeps the bandwidth in the desired range of 4.49MHz to 20.7MHz, as required in the Homeplug specification. The automatic gain control (AGC) scales the signal for conversion from analog to digital. The scaling maintains the optimum signal level at the ADC input, and keeps the AGC amplifiers out of saturation. The 50MHz, 10-bit ADC samples the analog signal and converts it to a 10-bit digital stream. The block fully integrates reference voltages and biasing for the input differential signal. Transmit Channel The transmit channel consists of a 10-bit digital-to-analog converter (DAC), a low-pass filter, and a transmitter buffer and line driver. The DAC receives the data stream from the Digital PHY IC through the MUX block. The 50MHz, 10-bit DAC provides the complimentary function to the receive channel. The DAC converts the 10-bit digital stream to an analog voltage at a 50MHz rate. The low-pass filter removes spurs and harmonics adjacent to the desired passband to help reduce the out of band transmitted frequencies and energy from the DAC output. The filter allows the MAX2980 to meet the Homeplug Alliance Specification. The transmit buffer and line driver blocks allow the output level of the low-pass filter to obtain a level necessary to connect directly to the powerline medium, without the use of external amplifiers and buffers. The output level is adjustable between 0.5VRMS and 0.75VRMS. The line driver can drive resistive loads as low as 10. There are some repeted sentence, remove them all! Digital Interface The digital interface is composed of some control signals and a 10-bit bi-directional data bus for the DAC and ADC. The control signals include a reset line, a transmit request, an I/O detection request, and a shutdown control. Control Signals Transmit Enable (ENTX) The ENTXline is used to enable the transmitter of the MAX2980 AFE circuit. With ENTXand ENREADdriven high, data sent to the DAC through DAD[9:0] is conditioned and delivered onto the power line. Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 6 Read Enable (ENREAD) The ENREAD line sets the direction of the data bus DAD[9:0]. With ENREAD high, data is sent from the Digital PHY to the DAC in the MAX2980 AFE. A low on ENREAD sends data from the ADC to the Digital PHY. Receiver Powerdown (/SHRCV\) The /SHRCV\ line provides receiver shutdown control. A logic high on /SHRCV\ powers down the receiver section of the MAX2980 whenever the device is transmitting. The MAX2980 also features a transmit power savings mode which reduces supply current from TBDmA to TBDmA. To enter the transmit power savings mode, drive /SHRCV\ high TBDs prior to the end of transmission. Connect /SHRCV\ to ENTXand ENREADfor normal operation. Digital-to-Analog and Analog-to-Digital Converter Input/Output. (DAD[9:0]) DAD[9:0] is the 10-bit bi-directional bus connecting the Digital PHY to the MAX2980 AFE DAC and ADC. The bus direction is controlled by ENREAD, as described in the Read Enable section. AGC Control Signal(CS) The CS signal controls the AGC circuit of the receive path in the MAX2980. A logic low on CS sets the gain circuit on the input signal to continuously adapt for maximum sensitivity. A valid preamble detected by the Digital PHY raises CS to high. While CS is high, the AGC continues to adapt for an additional short duration, then it locks the currently adapted level on the incoming signal. The Digital PHY holds CS high while receiving a transmission, and then lowers CS for continuous adaptation for maximum sensitivity of other incoming signals. AGC Freeze Mode (FREEZE) Use the FREEZE signal to lock the AGC gain. Note if CS or FREEZE is not used, the maximum loss in SNR is 1dB due to modulation effects generated by the AGC circuit on some selective channels. Clock (CLK) The CLK signal provides all timing for the MAX2980 AFE. Apply a 50MHz clock to this input. See timing diagram of figure 1 for more information. Reset Input (/RESETIN\) The /RESETIN\ signal provides reset control for the MAX2980. To perform a reset, set CLK in free running mode and drive /RESETIN\ low for a minimum of 100ns. Always perform a reset at powerup. Shutdown Control (SHDN) The MAX2980 features a low-power, shutdown mode that is activated by SHDN. Drive SHDN high to place the MAX2980 in shutdown mode. In shutdown, the MAX2980 consumes only TBDA. Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 7 tCLK 50MHz AFE CLK tADCO ADC DATA OUT tDACI DAC DATA INPUT Figure 1. ADC and DAC Timing Diagram MAX2980 Control Registers MAX2980 Serial Interface The 3 wire serial interface controls the MAX2980 AFE operation mode. The SCLK is the serial clock line for register programming. The SDI/O is I/O serial data input and output for register writing or reading. The SWR signal controls WRITE/READ mode of the serial interface. If SWR is HIGH the serial interface is in WRITE mode and new value can be written into AFE registers. Following SWR low-to-high transition, data are shifted synchronously to AFE ( LSB first ) register on the falling edge of the serial clock (SCLK) as illustrated in Figure 2. Note that one extra clock (WR_CLK) is required to write the content of holding buffer to the appropriate register bank. If SWR is LOW the serial interface is in READ mode and value of the current AFE register can be read. The Read operation to specific register must be followed right after writing to the same AFE register. Following SWR high-to-low transition, data are shifted synchronously to AFE ( LSB first ) register on the falling edge of the serial clock (SCLK) as illustrated in Figure 3. Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 8 SWR SDAT D0 D1 D2 D15 A0 A1 A2 SCLK WR CLK Figure 2. Writing AFE register timing diagram. SWR SDAT D0 D1 D2 D12 D13 D14 D15 SCLK Figure 3. Reading AFE register timing diagram. The MAX2980 has a set of six READ/WRITE registers, bits A2-A0 are the AFE register address bits. Table 1: AFE registers address: Register R1 (R/W) R2 (R/W) R3 (R/W) R4 (R/W) R5 (R/W) R6 (R/W) A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 MAX2980 AFE Register Maps Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 9 Table2. Register R1 Map Register Bit No. R1B0 R1B1 R1B2 R1B3 R1B4 R1B5 R1B6 R1B7 R1B8 R1B9 R1B10 R1B11 R1B12 R1B13 R1B14 R1B15 Default LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW Comment Active HIGH, power downs Receiver when in transmit mode. Based on /SHRCV\ signal going HIGH, (Enable SMT1 mode) Active HIGH, power down transmitter when in receive mode, based on XMT signal going High, (Enables SMT2 mode) Active HIGH, power down DAC when in Receive mode, based on XMT signal going HIGH (SMTDA mode) Active HIGH, power down entire chip For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes Note: From Bit 4 to Bit 15 control power down on various blocks. Table 3. Register R2 Map Register Bit No. R2B0 R2B1 R2B2 R2B3 R2B4 R2B5 R2B6 R2B7 R2B8 R2B9 R2B10 R2B11 R2B12 R2B13 R2B14 R2B15 Default LOW LOW LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW Comment For test purposes For test purposes For test purposes Active HIGH, bypass the HPF For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes For test purposes Active HIGH, bypass the receive LPF Note: From Bit 0 to Bit 2 and Bit 4 to B14 must be set to LOW to disable connection to the Test Bus. Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 10 Table 4. Register R3 Map Register Bit No. R3B0 R3B1 R3B2 R3B3 R3B4 R3B5 R3B6 R3B7 R3B8 R3B9 R3B10 R3B11 R3B [15:12] Default LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH 0111 Comment Set OFFSET DAC parameters. For test purposes. These set the pre-driver gain as follows setting 000 to 111: 3dB, 2dB, 1dB, 0dB, -1dB, -2dB, -3dB, -6dB R3B2 is the LSB Override process tune setting. For test purposes. Active HIGH, place process tune in continuous mode, otherwise active only during RESET Set to control the gain scaling in the DAC. For test purposes Table 5. Register R4 Map Register Bit No. R4B0 R4B1 R4B2 R4B3 Default LOW HIGH HIGH HIGH Comment Active HIGH, allow VADAPT continuous offset cancellation, otherwise offset cancellation stops on FREEZE = HIGH Active HIGH, allow HIGH to LOW transition of CS to control adaptation reset Active HIGH, enable 8us delay of offset cancellation FREEZE after FREEZE is active, otherwise delay = 0us. Active HIGH, enable freeze of VGA/OFFSET adaptation 20us (or 30us if en_30u is selected) after LOW to HIGH transition of CS `OR' on FREEZE input. When R4B3 is LOW, freeze will only take place on FREEZE HIGH. Active HIGH, enable adaptation energy detect to clear adaptation after loss of signal. When low this circuits disabled and CLR will be based on HIGH to LOW transition of CS. For test purposes. Load adaptation RMS target reference level M as follows: `00000' to `11111'. N = M+6 and level in RMS = sqrt (32N)/128 for N <= 32 and Level RMS = sqrt(128(N-24))/128 for N > 32. Default is N=32 or 250mVrms {ref_load} For test purposes For test purposes These two set the peak detector reference level as follows: `00' 0.15V, `11' 0.10V, `10' 0.18V, `01' 0.20V where R4B13 is the LSB. [For V1: "00" 0.2V, "11" 0.15V]. For test purposes R4B4 LOW R4B5 R4B [10:6] LOW 01011 R4B11 R4B12 R4B13 R4B14 R4B15 HIGH HIGH HIGH HIGH LOW Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 11 Table 6. Register R5 Map Register Bit No. R5B [6:0] R5B [12:7] R5B13 R5B14 R5B15 Default LOW LOW LOW LOW LOW Comment Set to control manually VGA & offset cancellation circuits. LOW for automatic adaptation. Table 7. Register R6 Map Register Bit No. R6B0 R6B [2:1] R6B3 R6B4 R6B [6:5] R6B7 R6B8 R6B9 R6B [11:10] R6B [13:12] R6B14 R6B15 Default LOW 00 LOW LOW 00 LOW LOW LOW 10 00 HIGH HIGH Comment For test purposes. ADC test only. For test purposes For test purposes Active HIGH, allow BYPASS of transmit LPF Used to set the parameter of VGA and DC offset cancellation algorithm. For test purposes. Applications Information Interfacing to Digital PHY Circuit The MAX2980 interfaces to a Homeplug 1.0 Digital PHY IC using a bi-directional bus to pass the digital data to and from the DAC and ADC. Handshake lines help accomplish the data transfer and operation of the MAX2980. The application circuit diagram of Figure 4 shows the connection of the MAX2980 to the digital PHY and the powerline. Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 12 DAD[9:0] ENREAD** ENTX** /SHRCV\ ** DIGITAL PHY CS* MAX2980 AFE FREEZE* PLIP POWER LINE HOT PLIN NEUTRAL POWER LINE INTERFACE HOST INT ERFACES PLOP PLON 50MHz CLK /RESETIN\ /SHDN\ * Signals are optional ** Signals can be connected to one contr ol line Clock Figure 4. Interfacing the MAX2980 to a Digital PHY Circuit and Power Line. Layout Considerations A properly designed PC board is an essential part of any high-speed circuit. Use controlled impedance lines on all frequency inputs and outputs. Use low inductance connections to ground on all ground pins and wherever the components are connected to ground. Place decoupling capacitors close to all VCC connections. For proper operation, connect the metal exposed paddle at the back of the IC to PCB ground plane with multiple vias. Chip Information Process: CMOS Transistor Count: TBD Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 13 Typical Application V DD 3 50 RECEIVER 10nF 50 1 22nF 1:1 10nF L HPF V DD 10nF* Spark Gap Power Line 4 2 22nF VDD 10 5k N DRIVER 10nF & 100nF 5k *10nF capacitor on Neutral is optional MAX2980 1.2nF 560pF 680pF 1 3 1 3 3.3 uH 4 1.2nF 560pF 680pF 2.7 uH HPF 4 2 2 Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 14 Package Information Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 15 Parameter Package Material Lead Surface Material Lead Base Material JC JA Maxim Confidential FA Description Sumitomo EME 6600CS (low stress compound) Solder Plate: 63% Sn, 37% Pb Copper Junction to Case Thermal Resistance Junction to Ambient Thermal Resistance, 0m/s air flow, no heat sink Value 7 C/W 37 C/W This information is subject to change without notice. MAX2980_DS_A Page 16 Maxim Confidential FA This information is subject to change without notice. MAX2980_DS_A Page 17 |
Price & Availability of MAX2980
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |